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Data Sheet August 1999
LG1600FXH Clock and Data Regenerator
Features
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Integrated clock recovery and data retiming Surface-mount package Single ECL supply Robust FPLL design Operation up to BER = 1e-3 SONET/SDH compatible loss of signal alarm High effective Q allows long run lengths Jitter tolerance exceeding ITU-T/Bellcore Low clock jitter generation: typical <0.005 UI Standard and custom data rates 0.50 Gbits/s--5.5 Gbits/s Complementary 50 I/Os
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Figure 1. LG1600FXH Open View
Applications
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SONET/SDH receiver terminals and regenerators OC-12 through OC-96/STM-4 through STM-32 SONET/SDH test equipment Proprietary bit rate systems Digital video transmission Clock doublers and quadruplers
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LG1600FXH Clock and Data Regenerator
Data Sheet August 1999
Regenerated clock and data are available from complementary outputs that can either be ac coupled, to provide 50 output match, or dc coupled with 50 to ground at the receiving end. The second-order PLL filter bandwidth is set by the user with an external resistor between pin 11 and ground (required). An internal capacitor provides sufficient PLL damping for most applications. In critical applications, PLL damping can be increased using an external capacitor between pins 9 and 11. The device is powered by a single -5.2 V ECL compatible supply and typically consumes 1.5 W. The LG1600FXH comes in standard bit rates, but can be factory tuned for any rate between 500 Mbits/s and 5500 Mbits/s. A test fixture (TF1004A) with SMA connectors is available to allow quick evaluation of the LG1600FXH.
Functional Description
The LG1600FXH Clock and Data Regenerator (CDR) is a compact, single device solution to clock recovery and data retiming in high-speed communication systems such as fiber-optic data links and long-span fiberoptic regenerators and terminals. Using frequency and phase-lock loop (FPLL) techniques, the device regenerates clean clock and error-free data signals from a nonreturn-to-zero (NRZ) data input, corrupted by jitter and intersymbol interference. The LG1600FXH exceeds ITU-T/Bellcore jitter tolerance requirements for SONET/SDH systems. The device houses two integrated circuits on an alumina substrate inside a hermetically sealed 3 cm x 3 cm (1.2 in. x 1.2 in.) surface-mount package: a GaAs IC that contains the high-speed part of an FPLL as well as a highly sensitive decision circuit; and a silicon bipolar IC that contains a loop filter, acquisition, and signal detect circuitry. The two ac-coupled complementary data inputs can be driven differentially as well as single ended. A dc feedback voltage V-FB maintains a data input threshold V-TH (decision level) that is optimum for a wide range of 50% duty cycle input levels (connect to V-TH). If needed, the user can supply an external threshold to compensate for different mark densities or distorted input signals (see Figure 10).
Theory of Operation
A digital regenerator has the task of retransmitting a bit stream that is received from a remote source with the same fidelity at which it was originally transmitted. Two basic properties of the digital signal need to be restored: the timing of the transitions between the bits and the value of each bit.
V-TH 51
V-FB 48
VSS V + OUT 43 38 V - OUT 35
1 k
0.047 F 50
0.047 F 25 k Q D D 31 26
V-IN V+IN
55 60
0.047 F
V + CLKO V - CLKO
0.047 F 65 1 k
50 25 k 0.047 F FREQ. & PHASE DETECT. 0 90 VCO
V+FB
LOOP CONTROL & SIGNAL DETECT 0.047 F 7 VREF 9 CEXT 11 REXT LOS
12-3225(F)r.6
Figure 2. LG1600FXH Block Diagram 2 Lucent Technologies Inc.
Data Sheet August 1999
LG1600FXH Clock and Data Regenerator
Theory of Operation (continued)
TO FLIP-FLOP
Consequently, the timing information that is present in the data needs to be extracted and a decision as to the value of each bit must be made. Both timing instant and decision levels are critical, since the economics of data transmission dictate the largest distance possible between transmitter and receiver. A practically closed data eye can therefore be expected at the output of the receiver, allowing only a small decision window. An added complication in nonreturn-to-zero (NRZ) systems is the absence of clock component in the data signal itself. Practical clock recovery circuits have used a combination of nonlinear processing to extract a spectral component at the clock frequency and narrowband filtering using a SAW filter or dielectric resonator. The relative bandwidth of such a filter must be on the order of a few tenths of a percent to minimize the data pattern dependence of the resulting clock. Temperature behavior of the passband characteristics, such as group delay, must be tightly matched to that of the data path. These extreme requirements make such a discrete design very difficult to manufacture at Gbits/s data rates. The LG1600FXH clock and data regenerator relies on phase-lock loop techniques, rather than passive filtering. The filter properties of a PLL are determined at low frequencies where parasitic elements play only a minor roll and stability is easily maintained. Furthermore, the reference frequency is determined by the data rate itself, rather than by the physical properties of a bandpass filter. Although PLLs can eliminate some of the shortcomings of passive bandpass filters used in clock recovery circuits, care was taken in the design of the LG1600FXH to preserve desired properties such as linearity of the jitter characteristics. A linear jitter transfer makes it a lot easier for the system designer to predict the overall performance of a link. As a result, the architecture chosen for the device is not basically different from the conventional clock recovery circuit. A transition detector extracts a pulse train from the incoming data signal which is used as a reference signal for a PLL. The transition pulse train can be seen as a clock signal that is modulated with the instantaneous transition density of the data signal. The PLL locks onto the frequency and phase of this pulse train and freewheels during times when transitions are absent. The LG1600FXH features dual phase detectors; one driven by an in-phase clock which is also driving the decision circuit flip-flop, the other is driven by a quadrature clock. The phase detectors produce a zero output when their respective clocks are centered with respect to the transition pulses. Lucent Technologies Inc.
DATA CIRCULATOR
TRANSITION PULSE PDI
0 FROM VCO PDQ 90
DELAYED DATA STUB LOGIC FPD OUT
12-3226(F)r.3
Figure 3. Frequency and Phase Detector For a transition pulse of half the width of the bit period, the timing diagram of Figure 4 shows how the in-phase clock ends up in the center of the data eye when the quadrature-phase detector output is forced to zero by the loop. The (patented) transition detector is comprised of an (active) circulator, a shorted stub, and an exclusive-OR gate. The circulator/stub combination produces a delayed version of the data. A transition at the input of the circuit results in an output pulse from the exclusive-OR gate whose width equals the return delay of the stub. The stub is tuned for a given bit rate and can be adjusted so that the in-phase clock is exactly centered in the error-free phase range of the retiming flip-flop.
T 1/2 T 1/4 T DATA
DELAYED DATA
TRANSITION PULSE
0 CLOCK
90 CLOCK
12-3227(F)r.2
Figure 4. Timing Diagram
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LG1600FXH Clock and Data Regenerator
Data Sheet August 1999
Theory of Operation (continued)
FPD OUT
FPD OUT
TIME
A. fck < fB
-360
-180
0
180
360 PHASE
FPD OUT
TIME
12-3228(F)r.4
Figure 5. Frequency and Phase Detector Characteristics
B. fck > fB
12-3229(F)r.4
Figure 6. Frequency Detector Operation The frequency detector is not a separate function but an integral part of the phase-lock loop. Any transition between frequency and phase acquisition is completely avoided. Figure 5 shows the output characteristics of the FPD, which is essentially an extended range phase detector. The two quadrature clock phases are used to produce hysteresis, which extends the phase detector range to 270. The extended range gives the phase detector a static frequency sensitivity as demonstrated in Figure 6. For clock frequencies lower than the bit rate (the phase is increasing), the top trajectory of the diagram in Figure 6 is followed. When the VCO frequency exceeds the bit rate, the lower trajectory applies. Since the linear part of the phase detector produces a netzero output, in the first instance, positive pulses are fed into the loop filter increasing the VCO frequency, while in the latter case, the FPD produces negative pulses. The wide, 540 range of the phase detector is also responsible for the high jitter tolerance of the LG1600FXH and an associated immunity to cycle slip under high jitter conditions. The clock can be momentarily misaligned as much as 270 but still return to its original position. This property is extremely important in synchronous systems, since a cycle slip would cause misalignment of the demultiplexer following the circuit resulting in a loss of frame condition. The LG1600FXH can handle bit error rates up to 1e-3 as a result of lowfrequency jitter.
PLL Dimensioning
The LG1600FXH CDR employs a heavily damped second order phase-lock loop. A linear model of this PLL is depicted in Figure 7. The conventional secondorder equation describing the jitter transfer of the PLL is shown below:
2 o 2ns + n H ( s ) = ----- ( s ) = ----------------------------------------2 2 i s + 2ns + n
where i and o denote the input and output phase, respectively, is the PLL damping ratio and n is the natural frequency. For most clock recovery applications a very high damping is required, that renders the PLL essentially as a first-order system with a slight peaking that is generally undesirable. The second-order equation above does not provide much insight into the peaking and bandwidth parameters.
i Ko Kd C PHASE DETECTOR Rx SUM OF INTERNAL AND EXTERNAL LOOP FILTER CAPACITANCE VCO o
12-3230(F)r.5
Figure 7. Phase-Lock Loop Linear Model
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Lucent Technologies Inc.
Data Sheet August 1999
LG1600FXH Clock and Data Regenerator
For moderate damping > 2.5 (b < 0.1), the -3 dB bandwidth of the PLL can be approximated by the loop gain pole product: JBW b = KdRxKo while the jitter peaking can be expressed in terms of the product of PLL bandwidth and loop filter time constant:
1 1 H ( s ) max 1 + --------- = 1 + ------------------------2 b Rx CKdKo
Theory of Operation (continued)
A more useful expression of the PLL characteristics is the following*:
1 b 1 + ----- s H ( s ) = ------------------------------------1 s + b 1 + ----- s
The jitter transfer is now directly expressed in the physical loop gain pole product, b, and the loop filter time constant, . Damping ratio, , and natural frequency, n, simply relate to these two parameters as follows:
= 0.5 b
and
n = n
As the last two expressions make clear, the PLL bandwidth is controlled by the value of the external resistor (see Figure 8), while the peaking depends both on the resistor value (quadratically) and total loop filter capacitance.
* Wolaver, D.H., Phase-Locked Loop Circuit Design, Prentice Hall, 1991.
1.2
3.6
10 C
1.0 10 C 0.8
JBW (MHz)
3.0 25 C 2.4
JBW (MHz)
25 C 0.6 70 C 0.4
1.8
70 C
1.2
0.2
0.6
0.0 0 50 100 Rx () 150 200 250
0.0 0 50 100 Rx () 150 200 250
A. LG1600FXH0622 (Cx = 0.15 F)
B. LG1600FXH2488 (Cx = 0)
12-3231(F)r.4--12-3232(F)r.4
Figure 8. Jitter Bandwidth vs. External Resistor Value
Lucent Technologies Inc.
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LG1600FXH Clock and Data Regenerator
Data Sheet August 1999
Pin Information
The pinout for the LG1600FXH is shown in Figure 9.
NIC GND GND V+FB GND GND GND GND V+IN GND GND GND GND V-IN GND GND GND 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
DNC GND GND DNC GND GND VREF GND CEXT GND REXT GND GND LOS GND GND DNC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35
V-TH GND GND V-FB GND GND GND GND V+OUT GND GND GND GND V-OUT GND GND VSS
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
NIC GND GND GND GND GND GND GND V-CLKO GND GND GND GND V+CLKO GND GND GND
12-3233(F)r.1
Figure 9. Pin Diagram
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Data Sheet August 1999
LG1600FXH Clock and Data Regenerator
Pin Information (continued)
The pin descriptions for the LG1600FXH are given in Table 1. Table 1. Pin Descriptions Pin 1, 4, 17 7 9 11 14 Symbol DNC VREF CEXT REXT LOS Name/Description Do Not Connect. Internal test point or reserved for future use. Reference Voltage. Nominally -3.2 V. Can be used to bias LG1605DXB (see data sheet). Load 10 k. Terminal for optional external capacitor to increase PLL damping (normally not connected). Terminal for external resistor to set PLL bandwidth (Required). Loss of Signal Indicator. Provides approximately 1 mA sink current with data signal present, can interface to CMOS, TTL when connected to logic VDD through a 10 k resistor. Normally grounded when not used. Recovered Clock Out. ac couple or terminate into 50 to GND. Recovered Clock Out. ac couple or terminate into 50 to GND. Supply Voltage. -5.2 Vdc nominal. Warning: Connecting a positive voltage to this pin will permanently damage the device. Regenerated Data Out. ac couple or terminate into 50 to GND. Regenerated Data Out. ac couple or terminate into 50 to GND. dc Feedback Voltage. Connect to V-TH. Input Threshold Voltage. Connect to V-FB. Negative Data Input. Internally ac coupled. Positive Data Input. Internally ac coupled. dc Feedback Voltage. Internally connected; not normally used. No Internal Connection. May be grounded. Ground. Connect to top ground plane of coplanar/microstrip circuit board.
26 31 35
V-CLKO V+CLKO VSS
38 43 48 51 55 60 65 18, 68 2, 3, 5, 6, 8, 10, 12, 13, 15, 16, 19, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 32, 33, 34, 36, 37, 39, 40, 41, 42, 44, 45, 46, 47, 49, 50, 52, 53, 54, 56, 57, 58, 59, 61, 62, 63, 64, 66, 67 Body
V-OUT V+OUT V-FB V-TH V-IN V+IN V+FB NIC GND
GND
Ground. Does not need to be connected. GND pins provide all necessary ground connections.
Lucent Technologies Inc.
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LG1600FXH Clock and Data Regenerator
Data Sheet August 1999
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Table 2. Absolute Maximum Ratings Parameter Supply Voltage Range (VSS) Loss of Signal Bias Voltage (VDD) Power Dissipation Voltage (all pins) Transient Voltage to ac Couple Pins (VIN, REXT) Storage Temperature Range Operating Temperature Range Min -7 -- -- VSS -- -40 -40 Max 0.5 7 2 0.5 3 125 100 Unit V V W V V C C
Recommended Operating Conditions
Table 3. Recommended Operating Conditions Parameter Case Temperature Power Supply Symbol tCASE VSS Min 0 -4.7 Max 70 -5.7 Unit C V
Handling Precautions
Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Lucent Technologies Microelectronics Group employs a human-body model (HBM) for ESD-susceptibility testing and protection design evaluation. The HBM (resistance = 1500 , capacitance = 100 pF) is used. The HBM ESD threshold presented in Table 4 was obtained by using these circuit parameters. Table 4. ESD Threshold HBM ESD Threshold Device LG1600FXH Voltage 200 V
Mounting and Connections
Certain precautions must be taken when using solder. For installation using a constant temperature solder, temperatures of under 300 C may be employed for periods of time up to 5 seconds, maximum. For installation with a soldering iron (battery operated or nonswitching only), the soldering tip temperature should not be greater than 300 C and the soldering time for each lead must not exceed 5 seconds.
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Lucent Technologies Inc.
Data Sheet August 1999
LG1600FXH Clock and Data Regenerator
Electrical Characteristics
tCASE = 0 C to 70 C, VSS = -4.7 V to -5.7 V, VDD = 5 V, bit rate = fB Gbits/s 0.05% NRZ and data pattern = 223 - 1 PRBS, 200 mV VIN 800 mV, BER < 1e-9, unless otherwise indicated. Note: Minimum and maximum values are testing requirements. Typical values are characteristics of the device and are the result of engineering evaluations. Typical values are for information purposes only and are not part of the testing requirements. Parameter Symbol Conditions Data Input Voltage V-IN Single ended on either input Data Input Voltage V+IN - V-IN Differential ac coupled Data Output Voltage VOUT Data Output Voltage VOUT dc coupled Clock Output Voltage VCLKO dc coupled ac coupled; fB 3 Gbits/s Clock Output Voltage VCLKO Clock Output Voltage VCLKO ac coupled; fB > 3 Gbits/s Output Pulse Width RelaPW% tCASE = 40 C tive to Bit Period T = 1/fB Clock Output Duty Cycle DCCLKO tCASE = 40 C Clock/Data Output Transitr, tf 20% to 80% tion Time Maximum Bit Error Rate BERMAX Jitter modulation @ fB x 40 kHz, tCASE = 40 C LOS Output Voltage, Low VLOSL RL = 10 k LOS Output Voltage, High VLOSH RL = 10 k, V-IN = 0 V Loss of Signal Delay Jitter Generation Jitter Transfer Bandwidth Output Reference Voltage Jitter Tolerance LOS JGEN JBW VREF JTOL Measured from last data transition, tCASE = 40 C -- User adjustable with RX as suggested by Figure 8, tCASE = 25 C Load to ground 20 k fmod fB x 40 kHz, tCASE = 40 C fB x 40 kHz fmod fB x 400 kHz, tCASE = 40 C fmod fB x 400 kHz, tCASE = 40 C Measured from first data transition*, tCASE = 40 C -5.7 V VSS -4.7 V Min 200 200 625 650 650 625 500 90 40 -- 1e-3 -1 VDD - 0.5 10 -- -- -3.4 1.5 0.6 fB/ fmod 0.15 -- -- Typ -- -- 750 800 750 750 600 100 -- 80 -- -0.8 VDD 30 0.005 fB -3.15 5 2 fB/fmod 0.5 600 290 Max 800 1600 900 900 900 900 900 110 60 100 -- 0.5 VDD 100 0.01 -- -2.9 -- -- -- 800 320 Unit mVp-p mVp-p mVp-p mVp-p mVp-p mVp-p mVp-p % % ps -- V V s UI MHz V UI UI UI s mA
Acquisition/Recovery Time Supply Current
ACQ ISS
* Parameter guaranteed by design or characterization and not production tested.
Lucent Technologies Inc.
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LG1600FXH Clock and Data Regenerator
Data Sheet August 1999
Test Circuit
+
500 k ALTERNATIVE V-TH 51
OPTIONAL THRESHOLD CONTROL
50
50
OPTIONAL Ca > 0.1 F/fB + VSS 5.2 V VSS 35
V-FB 48
V+OUT 43 38
V-OUT
1 k
0.047 F 50
25 k
0.047 F
OPTIONAL Cb > 100 pF/fB 31 V + CLKO 26 V - CLKO 50 50
V-IN 50 50 V+FB V+IN
55 60
0.047 F
D D 0.047 F 50 25 k 0.047 F
Q
65
1 k
FREQ. & PHASE DETECT.
0 90 VCO
DATA GENERATOR
LOOP CONTROL & SIGNAL DETECT 0.047 F 7 VREF 9 CEXT 11 REXT 14 LOS VLOS 10 k CX OPTIONAL (SEE TEXT) RX = 140 REQUIRED VDD + 5V
12-3234(F)r.6
Notes: Resistor RX determines the PLL bandwidth and is required for normal operation. The LG1600FXH differs in this respect from the LG1600AXD CDR, which has an internal resistor that sets a minimum bandwidth. The recommended value is 140 for optimal jitter transfer performance. Capacitor CX is optional and can be used to increase the damping of the PLL in critical applications. The outputs may be either ac coupled, as indicated, or dc terminated into 50 . In the first case, good output return loss can be obtained. The latter configuration provides a 0 mV to -800 mV output swing for easy interface to dc-coupled circuits.
Figure 10. LG1600FXH Typical Test Circuit
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Lucent Technologies Inc.
Data Sheet August 1999
LG1600FXH Clock and Data Regenerator
Typical Performance Characteristics
LG1600FXH0553
LG1600FXH2488
LG1600FXH4977
Figure 11. LG1600FXH Typical Eye Patterns
Lucent Technologies Inc.
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LG1600FXH Clock and Data Regenerator
Data Sheet August 1999
Typical Performance Characteristics (continued)
VOUT
V+CLKO
OUTPUT TIMING
500
400 OUTPUT TIMING (ps)
300
200
100 y = 1/4x - 65 0
-100 0 500 1000 BIT PERIOD (ps)
12-3235(F)r.2
1500
2000
Figure 12. Data Clock Output Timing Diagram
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Lucent Technologies Inc.
Data Sheet August 1999
LG1600FXH Clock and Data Regenerator
Typical Performance Characteristics (continued)
BLANKING PULSE INPUT DATA OUTPUT DATA ERROR SIGNAL
ERROR RECOVERY TIME
700 600 500 400 300 200 100 0 0 200 400 600 800 1000 INPUT BLANKING (s)
12-3236(F)r.3
RECOVERY TIME (s)
Figure 13. Error Recovery Timing Diagram
Lucent Technologies Inc.
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LG1600FXH Clock and Data Regenerator
Data Sheet August 1999
Typical Performance Characteristics (continued)
DATA BLNK CLK PATTERN GENERATOR DATA IN DATA OUT CLK OUT MIXER CLK DATA ERROR DETECTOR CH2 CH3 DIGITIZING OSCILLOSCOPE
CH1
OUT PULSE GENERATOR TRIG
CH3
CH2
CH1
LF OSCILLOSCOPE
12-3237(F)r.4
Figure 14. Error Recovery Test Circuit
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Lucent Technologies Inc.
Data Sheet August 1999
LG1600FXH Clock and Data Regenerator
Outline Diagram
68-Pin Surface-Mount Package
Dimensions are in inches.
1.180 0.590
68 1
52 51
0.050 TYP
R0.020 0.158 0.015 TYP 17 18 35 34 0.010 +0.005 -0.002 0.030 DETAIL A 0--5
1.370 0.10
0.010
DETAIL A
12-3350(F).ar.1
Lucent Technologies Inc.
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LG1600FXH Clock and Data Regenerator
Data Sheet August 1999
Ordering Information
Device Code LG1600FXHXXXX LG1600FXH0500 LG1600FXH0553 LG1600FXH0622 LG1600FXH1200 LG1600FXH1244 LG1600FXH1298 LG1600FXH1555 LG1600FXH2380 LG1600FXH2433 LG1600FXH2488 LG1600FXH2666 LG1600FXH2949 LG1600FXH3111 LG1600FXH3840 LG1600FXH4977 LG1600FXH5332 TF1004A Package Surface-Mount Package Surface-Mount Package Surface-Mount Package Surface-Mount Package Surface-Mount Package Surface-Mount Package Surface-Mount Package Surface-Mount Package Surface-Mount Package Surface-Mount Package Surface-Mount Package Surface-Mount Package Surface-Mount Package Surface-Mount Package Surface-Mount Package Surface-Mount Package Surface-Mount Package Test Fixture Temperature 0 C to 70 C 0 C to 70 C 0 C to 70 C 0 C to 70 C 0 C to 70 C 0 C to 70 C 0 C to 70 C 0 C to 70 C 0 C to 70 C 0 C to 70 C 0 C to 70 C 0 C to 70 C 0 C to 70 C 0 C to 70 C 0 C to 70 C 0 C to 70 C 0 C to 70 C -- Comcode 107236143 107914038 107236101 107339244 107841447 107386179 107236127 107914046 107236135 107645939 107081879 107386187 107385650 107394132 107840423 107081887 107081895 106497621
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Lucent Technologies Inc.
Data Sheet August 1999
LG1600FXH Clock and Data Regenerator
Appendix
The test fixture mentioned in the data sheet is sold separately and is described in detail below.
5-7831(F)
Figure 15. TF1004A Test Fixture
TF1004A Test Fixture Features
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SMA connectors Easy package placement Good RF performance
Test Fixture Functional Description
The TF1004A test fixture is used to characterize 68-pin surface-mount packages for high-speed fiber-optic communications. The fixture consists of a metallized substrate (PTFE filled material) fastened to a brass base with RF connectors and mounting hardware for the package. The package leads make contact to the circuit traces on the fixture through use of a pressure ring and four finger nuts. The TF1004A is preassembled and fully tested prior to shipment.
Before Use of Test Fixture
s s s
Due to possible stress during shipment, SMA connectors may be misaligned. Check each SMA for continuity. If necessary, realign and retighten with a 5/64 in. hex key wrench.
Lucent Technologies Inc.
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LG1600FXH Clock and Data Regenerator
Data Sheet August 1999
Appendix (continued)
Instructions for Use of Test Fixture
A pair of flat-tip tweezers can be used to insert or remove a package from the test fixture. Always wear a grounding strap to prevent ESD. 1. To insert a package, remove the four finger nuts and gently lift the pressure ring off of the test fixture. 2. Place the pressure ring, cavity side up, on a flat ESD safe surface. 3. Connect the metal tube to any general-purpose vacuum source with flexible tubing. The vacuum source should be off. 4. Place the package, lid down, on a flat ESD safe surface. Locate pin 1 on the package. 5. Insert the package into the pressure ring (lid down) with pin 1 located next to the orientation mark and turn on the vacuum. The vacuum will retain the package in the pressure ring during the following steps. 6. Align the vertically conductive material on the circuit board. 7. Place the pressure ring down over the alignment pins and gently tighten the finger nuts. 8. Remove vacuum, if desired. The vacuum source tubing can be removed for convenience.
V-FB (48)
V+OUT V-OUT (43) (38)
VSS (35)
V-TH (51) V-IN (55) V+IN (60) V+FB (65) PIN #1 DNC (1) DNC (4) DNC (17) LOS (14) V+CLK (31) V-CLK (26) NIC (18)
(7) VREF
(9) CEXT
(11) REXT
NIC = NO INTERNAL CONNECTION DNC = DO NOT CONNECT (##) = PACKAGE PIN NUMBER
5-7832(F)r.1
Figure 16. TF1004A Connector Assignment
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Lucent Technologies Inc.
Data Sheet August 1999
LG1600FXH Clock and Data Regenerator
Notes
Lucent Technologies Inc.
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LG1600FXH Clock and Data Regenerator Interactive Terminal Transmission Convergence
Preliminary Data Sheet August 1999
For additional information, contact your Microelectronics Group Account Manager or the following: http://www.lucent.com/micro INTERNET: docmaster@micro.lucent.com E-MAIL: N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P. R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information.
Copyright (c) 1999 Lucent Technologies Inc. All Rights Reserved Printed in U.S.A.
August 1999 DS99-186HSPL (Replaces DS96-237FCE)

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